1. Field of the Invention
The present invention relates to a slew rate calibrating circuit and a slew rate calibrating method to adjust a slew rate being a maximum change rate of a voltage of a signal to be output, at high speed, from circuits such as a semiconductor device and more particularly to the slew rate calibrating circuit and slew rate calibrating method suitably used to adjust the slew rate to become its desired value.
The present application claims priority of Japanese Patent Application No. 2005-056472 filed on Mar. 1, 2005, which is hereby incorporated by reference.
2. Description of the Related Art
For example, when a rectangular pulse signal represented by a binary number of a “0” or a “1” is output, at high speed, from an output buffer of an LSI (Large Scale Integrated circuit) to a transmission path connected to the LSI, noises occur, in some cases, due to reflections of a signal or a like occurring when the signal is input to a rear-stage circuit. Such noise causes a malfunction of the rear-stage circuit. To solve this problem, calibration of a slew rate is generally performed to suppress a steep rise or fall of a waveform of a pulse signal. Here, a slew rate denotes an absolute value of a voltage change rate of a signal which is represented by a voltage that can increase per unit time.
A slew rate of a signal to be sent out, at high speed, to a transmission path has a proper range of a value. For example, if a slew rate is made excessively small, a voltage change of a signal is very slow and, as a result, a delay time occurring before a voltage of the signal reaches a specified voltage becomes longer. If a slew rate is made excessively large, a response to a voltage change is excellent, however, as described above, the excessively large slew rate causes occurrence of noises.
To solve this problem, a slew rate calibrating circuit is conventionally proposed (first conventional technology) which is so configured as to adjust a slew rate to become its proper value determined empirically depending on a length of a transmission path or a state of a signal to be output to the transmission path (see Japanese Patent Application Laid-open No. 2002-26712, 0019-th paragraph, FIGS. 3 and 6 (Patent Reference 1)). In the above Patent Reference 1, an output buffer to output a signal to a transmission path is used to adjust a slew rate. Then, a simulation is performed on correlation between a parameter to be used for the slew rate calibration and a slew rate to identify a value of the parameter. This enables the slew rate to be adjusted to become its target value.
However, ordinarily, the correlation between a slew rate and a parameter differs slightly depending on a factor of a difference in configurations of an output buffer to be applied or a difference in use environments. Therefore, the technology disclosed in the above Patent Reference 1 has a problem in that a slew rate cannot be adjusted with high accuracy.
To solve this problem, a method is considered to be available in which a slew rate is made to coincide with its target value by calculating a maximum voltage value to be changed in a unit time of a signal to be output from an output buffer and by changing a parameter until an amount of the change coincides with a calculated value. However, it is necessary that the unit time to be employed in the above operations is set to be shorter than, at least, one cycle period in a transfer frequency, and the higher the target value of a slew rate is, the shorter the unit time becomes.
As a method for accurately measuring a very short unit time, a second conventional technology is disclosed (see, for example, Japanese Patent Application Laid-open No. 174594, 0046-th paragraph, FIG. 4 (Patent Reference 2)) in which two clocks each having a different frequency are used. In the above Patent Reference 2, a first clock having a first period and a second clock having a second period extended by a specified time than the first period are prepared and the first clock is first input through a variable delay circuit to a specified device. Then, a delay time of the variable delay circuit is set so that a delay time of a clock output from the device relative to the original first clock comes near the first period. That is, a sum total of the delay time occurring between an input side of the variable delay circuit and an output side of the device is made to coincide with a first period. With a state of the above coincidence, a clock to be input to the specified device through the variable delay circuit is switched to select the second clock. This causes the delay time of the clock to be output from the device relative to the second clock to be made equal to the first period. That is, a difference in phase between the clock to be output from the device and the original second clock becomes equal to the above-described specified time. Thus, it is made possible to measure, with high accuracy, a very short unit time to be used as a reference when a slew rate is made to coincide with its target value.
However, according to the above second conventional technology, in order to make a slew rate of a signal output from the output buffer to a transmission path come near its target value, not only detection of an amount of a change in a voltage within the measured unit time but also measurement of a unit time in a period of time during which the amount of the change of a voltage value takes on a maximum value is required. As described above, the unit time for setting a slew rate is very short and it is almost impossible for a user to properly choose the starting and terminating timing.